/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  SpiSlave_Ip
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL SpiSlave_Slave plugins.
 */

#ifndef SPI_SLV_IP_H_
#define SPI_SLV_IP_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "SpiSlave_Mld.h"

#define  SPI_SLV_PIPE_LINE_SIZE_8B 3U
#define  SPI_SLV_PIPE_LINE_SIZE_4B 4U
#define  SPI_SLV_PIPE_LINE_SIZE_2B 5U
#define  SPI_SLV_PIPE_LINE_SIZE_OB 2U

#define  SPI_SLV_DATA_WIDTH_MIN 4U
#define  SPI_SLV_DATA_WIDTH_MAX 32U
#define  SPI_SLV_FREAM_SIZE_MAX 1024U
#define  SPI_SLV_FREAM_SIZE_MIN 1U
#define  SPI_SLV_CLK_PRESSCALE_MAX 0xFFU
#define  SPI_SLV_IDLE_COUNT_MAX 0x1FU
#define  SPI_SLV_TIMEOUT_COUNT_MAX 0x1FU
#define  SPI_SLV_POL_VEL_MAX 0xFU
//2 mst_idle 3 mst_start  7 mst_data wait
#define  SPI_SLV_FSM_WAIT_DATA_STA 7U
#define  SPI_SLV_FSM_M_STR_STA 3U
#define  SPI_SLV_FSM_IDLE_STA 2U
#define  SPI_SLV_BAUD_RATE_MAX  50000000U
#define  SPI_SLV_FIFO_LEN       16U
#define  SPI_SLV_BAUD_RATE_US  50U
#define  SPI_SLV_MIN_WAIT_US  5U

#ifndef ROUNDUP
#define ROUNDUP(a, b) (((a) + ((b)-1)) & ~((b)-1))
#endif
#ifndef ROUNDDOWN
#define ROUNDDOWN(a, b) ((a) & ~((b)-1))
#endif

#define SPISLV_IS_ALIGNED(a, b)    \
        ((boolean)((uint32)0 == (  ((uint32)(a)) & (((uint32)(b))-1U))))

enum spi_slv_dev_flags {
    F_SLV_DEV_LSB  = 0x01U,
    F_SLV_DEV_NSS_HIGH = 0x02U,
    F_SLV_DEV_IS_BE = 0x04U,
    F_SLV_DEV_BAUDRATE_CHK = 0x10U,
    F_SLV_DEV_PARITY_CHK = 0x20U,
    F_SLV_DEV_TIMEOUT_CHK = 0x40U,
};

enum spi_slv_bus_flags {
    SPI_SLV_SSP_MODE_ENABLE = 0x01u,
    SPI_SLV_DMA_RX_ENABLE = 0x02u,
    SPI_SLV_DMA_TX_ENABLE = 0x04u,
    SPI_SLV_MODE_SLAVE_ENABLE = 0x08u,
    SPI_SLV_HALF_DUPLEX_ENABLE = 0x10u,
    SPI_SLV_TX_IRQ_ENABLE = 0x20u,
    SPI_SLV_RX_IRQ_ENABLE = 0x40u,
    SPI_SLV_CS_IRQ_ENABLE = 0x80u,
};

struct spi_slv_dev_priv {
    enum spi_slv_tim_mode   mode;
    uint32              flags;
    uint8               width;
    uint8               nss_idx;
    uint8               timeout;
    uint8               parity;
    uint32              baudratechk;

};

struct spi_slv_bus_priv {
    uint32                    flags;
    void                       *dma_ch_rx;
    void                       *dma_ch_tx;
    uint32                    dma_err;
};


#define  SPI_SLAVE_MAX_TIMEOUT_SWRST 2560U
#define  SPI_SLAVE_INTERRUPT_MODE  (SPI_SLV_CS_IRQ_ENABLE|SPI_SLV_RX_IRQ_ENABLE|SPI_SLV_TX_IRQ_ENABLE)
extern const struct mld_spi_slv_ops semidrive_spi_slv_bus_ops;

#ifdef __cplusplus
}
#endif

#endif
